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rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5035a/b - 02 february 2017 www.richtek.com 1 7 +3 channel dc - dc converters with rtc and i 2 c interface general description rt 5035a/b is a highly - integrated dsc power management ic that contains 7ch switching dc - dc converters and two generic ldos, one keep - alive low - quiescent ldo for rtc, one load switch with soft - start control and current limit, a switch with reverse leakage prevention for backup battery, and a real - time - clock (rtc) including time counter and 32768hz oscillator. the dc - dc converters are one low - voltage step - up operated in either async - pfm or sync - pwm, one current mode sync step - up/down (buck - boost), four sync step - down, and one asyn step - up for wled driver. all power mos are integrated. and compensation networks are built in. rt 5035a/b uses i 2 c interface to set power - on and power - off timing, output voltage, and wled current and dimming level, and also access rtc time cou nters and oscillator fine - tuning. rt 5035a/b dedicate for cmos image sensor application by providing one sync step - down , one ldo, and one load switch. the rt 5035a/b also provides rich protection functions include over - current protection, under - voltage protection, over - voltage protection, over - temperature protection, and over - load protection. rt 5035a/b is available in w qfn - 40 l 5x5 package . applications ? digital camera s ? portable instruments features ? ch1 sync step - up in pwm mode or async step - up in pulse frequency mode ? ch2 current mode sync step - up/down ? ch3/ch4/ch5 current mode sync step - down ? sw4 load switch with soft - start inrush control and current limit ? ch6 generic low voltage ldo for cmos sensor ? ch7 wled driver in async step - up mode ? open led protection ? 32 dimming levels ? ch8 generic low voltage ldo for multiple purpose power supply ? ch9 keep - alive low - quiescent ldo ? ch10 sync step - down or async step - down in pulse frequency mode for memory standby mode application ? lv sync step - down dc - dc converter high efficiency up to 95% ? 100% (m ax) duty cycle for ch3, ch4, ch5 &ch10 ? i 2 c control interface t o program enable , power on/off delay time, output regulated voltage , wled dimming current ? rtc timer and oscillator ? fixed 2mhz switching frequency for c h 1 , ch3, ch4, ch5, ch10 ? fixed 1mhz switching frequency for c h 2, c h 7 simplified application circuit r t 5 0 3 5 a / b v o u t 1 v o u t 2 v o u t 3 v o u t 5 v o u t 4 s w o l x 7 v o u t 8 r t c p w r v o u t 1 0 b a t i 2 c c o n t r o l s c l e n s y n c v d d m s d a c 3 2 k g n d v o u t 6 r e s e t s t e p - u p f o r m o t o r s t e p - u p / d o w n f o r i / o s t e p - d o w n f o r c o r e s t e p - d o w n f o r c m o s l o a d s w i t c h f o r c m o s s t e p - d o w n f o r c m o s l d o f o r c m o s s t e p - u p f o r l e d b a c k l i g h t l d o f o r h d m i l d o f o r r t c s t e p - d o w n f o r m e m o r y
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5035a/b - 02 february 2017 2 ordering information note : richtek products are : ? rohs compliant and compatible with the current requirements of ipc/jedec j - std - 020. ? suitable for use in snpb or pb - free soldering processes . marking information pin configuration (top view) wqfn - 40l 5x5 functional pin description pin no. pin name pin function 1 lx1 switch n ode of ch1. this pin is in high impedance during shutdown. 2 open drain output port to assert the status of monitored vddm voltage. 3 fb7 feedback input pin for ch7. this pin is in high impedance during shutdown. 4 vout6 regulated output node of ch6 generic ldo. when turning off, rt 5035a/b would discharge ch6 output capacitors internally till vout6 < 0.1v. this pin is in high impedance during shutdown. 5 pvdd6 power i nput of ch6 g eneric ldo. this pin is in high impedance during shutdown. 6 lx7 switch n ode of ch7. this pin is in high impedance during shutdown. 7 lx4 switch n ode of ch4. this pin is in high impedance during shutdown. 8 pvdd4/10 power input pin of ch4 and ch10. this pin is in high impedance during shutdown. r t 5 0 3 5 a / b p a c k a g e t y p e q w : w q f n - 4 0 l 5 x 5 ( w - t y p e ) l e a d p l a t i n g s y s t e m g : g r e e n ( h a l o g e n f r e e a n d p b f r e e ) a : l i - i o n b : 2 a a a l k a l i n e r t 5 0 3 5 a g q w y m d n n r t 5 0 3 5 a g q w : p r o d u c t n u m b e r y m d n n : d a t e c o d e r t 5 0 3 5 a g q w r t 5 0 3 5 b g q w y m d n n r t 5 0 3 5 b g q w : p r o d u c t n u m b e r y m d n n : d a t e c o d e r t 5 0 3 5 b g q w l x 1 v o u t 6 f b 7 v n e g l x 1 0 p v d d 4 / 1 0 l x 4 p v d d 6 l x 7 l x 3 v o u t 5 / f b 5 v o u t 8 l x 2 b e n l x 2 a p v d d 2 p v d d 5 l x 5 p v d d 8 c n c p b a t v o u t 4 / s w i v o u t 1 0 / f b 1 0 s w o s d a s c l v o u t 2 s e q v o u t 1 s y n c v d d m r t c p w r x i n x o u t r t c g n d v o u t 3 / f b 3 p v d d 3 c 3 2 k r e s e t 1 2 3 4 5 6 7 8 9 1 0 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 g n d reset
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5035a/b - 02 february 2017 www.richtek.com 3 pin no. pin name pin function 9 lx10 switch n ode of ch10. this pin is in high impedance during shutdown. 10 vneg output node of n egative c harge p ump to enhance ch2 (pvdd2 ? ? lx2a ), ch3, ch4, ch5, ch10 pmos driving. the regulated voltage is the higher one between (bat ? 4.5v) and ( ? bat). when the n egative c harge p ump is off, vneg is internally connected to gnd. connect this pin to an external 1 ? f capacitor. 11 cn negative s witch node of c harge p ump. a fly capacitor is needed between pin cp and cn. 12 cp positive s witch node of c harge pump. 13 bat battery power input and sense pin. recommend that input bypass capacitors are as close as possible to the ic. the ic would sense the voltage of this pin for uvlo and perform body - diode direction control of ch1 pmos switches. this pin is also the power inpu t pin of negative charge pump circuit for vneg. 14 vout4/swi sense pin for ch4 output voltage and power pin for load switch sw4. when turning off, rt 5035a/b would discharge ch4 output capacitors internally till vout4 < 0.1v. recommend that output capacitors are as close to rt 5035a/b as possible. this pin is in high impedance during shutdown. 15 vout10 /fb10 sense p in of ch 10 o utput v oltage. this pin is also the feedback pin for vout 10 if i 2 c is set to use the external resistor. when turning off, the ic discharges ch 10 output capacitors internally until vout 10 < 0.1v. recommend that output capacitors are as close as possible to the ic. this pin is in high impedance during shutdown. 16 swo power switch output pin of load switch sw4. when turning off, rt 5035a/b would discharge swo output capacitors internally. this pin is in high impedance during shutdown. 17 sda data i nput and output p in for the i 2 c s erial p ort. 18 scl clock i nput p in for the i 2 c s erial p ort. 19 vout2 power output pin for ch2 output voltage. when turning off, rt 5035a/b would discharge ch2 output capacitors internally till vout2 < 0.1v. i 2 c interface power level must be equal to c h 2 output voltage. this pin is in high impedance during shutdown. 20 seq sequence s etting pin. 21 lx2b switch n ode b of ch2. this pin is in high impedance during shutdown. 22 en enable input pin to activate the rt 5035a/b power on (en = high) and off. rt 5035a/b includes an internal pull - low at en pin. 23 lx2a switch n ode a of ch2. this pin is in high impedance during shutdown. 24 pvdd2 power input pin of ch2 and it must connect to the same node as bat. this pin is in high impedance during shutdown. 25 lx5 switch n ode of ch5. this pin is in high impedance during shutdown. 26 pvdd5 power input pin of ch5. pvdd5 could be separated from bat. and the logic low level for pmos is automatically selected. (vneg or gnd) this pin is in high impedance during shutdown. 27 vout5 /fb5 sense p in of ch5 output voltage. this pin is also the feedback pin for vout5 if i 2 c is set to use the external resistor. when turning off, the ic discharges ch5 output capacitors internally until vout5 < 0.1v. recommend that output capacitors are as close as possible to the ic. this pin is in high impedance during shutdown.
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5035a/b - 02 february 2017 4 pin no. pin name pin function 28 vout8 regulated output node of ch8 generic ldo. when turning off, rt 5035a/b would discharge ch8 output capacitors internally till vout8 < 0.1v. this pin is in high impedance during shutdown. 29 pvdd8 power input node of ch8 generic ldo. this pin is in high impedance during shutdown. 30 lx3 switch n ode of ch3. this pin is in high impedance during shutdown. 31 c32k rtc 32768hz clock output pin. its rails are vddm and gnd. when goes low, c32k output s low. 32 pvdd3 power input pin of ch3 and it must connect to the same node as bat. this pin is in high impedance during shutdown. 33 vout3 /fb3 sense p in of ch 3 o utput v oltage. this pin is also the feedback pin for vout 3 if i 2 c is set to use the external resistor. when turning off, the ic discharges ch 3 output capacitors internally until vout 3 < 0.1v. recommend that output capacitors are as close as possible to the ic. this pin is in high impedance during shutdown. 34 rtcgnd ground pin for rtc timer counter and oscillator. 35 xout crystal o utput. this pins parasitic capacitance should be kept as low as possible. noise interference should also be avoided. 36 xin crystal i nput. this pins parasitic capacitance should be kept as low as possible. noise interference should also be avoided. 37 rtcpwr rtcldo power pin. connect this pin to a backup battery 38 vddm regulation voltage output of ch9 keep - alive ldo. it also provides power for all ic control circuit. 39 sync pll s ynchronous i nput p in . 40 vout1 power output and sense pin for ch1 output voltage. recommend that output capacitors are as close to rt 5035a/b as possible. this pin is in high impedance during shutdown. 41 (exposed pad) gnd rt 5035a/b power ground and control circuit ground. exposed pad should be soldered to pcb and connected to gnd. reset
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5035a/b - 02 february 2017 www.richtek.com 5 functional block diagram f b 7 l x 7 v d d m c h 6 g e n e r i c l d o - + p v d d 6 v o u t 6 v r e f & d a c c h 5 l v c - m o d e s y n c . s t e p - d o w n + - v r e f & d a c l x 5 p v d d 5 v d d m b a t u v l o 2 . 6 v / 2 . 4 v ( p a r t a ) o r 1 . 7 v / 1 . 5 ( p a r t b ) v o u t 5 / f b 5 l x 4 c h 4 l v c - m o d e s y n c . s t e p - d o w n + - p v d d 4 / 1 0 v d d m v n e g v o u t 4 / s w i c h 3 l v c - m o d e s y n c . s t e p - d o w n + - p v d d 3 l x 3 v d d m v o u t 3 / f b 3 v n e g c h 2 l v c - m o d e s y n c . s t e p - u p / d o w n l x 2 a p v d d 2 v d d m + - v r e f & d a c v n e g v o u t 2 l x 2 b c h 1 p f m a s y n c . o r c - m o d e s y n c . l v s t e p - u p l x 1 v o u t 1 v d d m + - v r e f & d a c ( w / d v s ) v o u t 1 b a t c h 8 g e n e r i c l d o + - v o u t 8 p v d d 8 c h 9 l d o k e e p a l i v e 3 . 1 v a l w a y s o n v m v d d m r e v e r s e l e a k a g e c o n t r o l r e s e t 2 . 4 v / 2 . 2 v r t c p w r v n e g c h a r g e p u m p v n e g = b a t - 4 . 5 v x i n x o u t r t c g n d r e g i s t e r f i l e o u t p u t v o l t a g e , p o w e r o n / o f f s e q u e n c e c o n t r o l , d e l a y t i m e , w l e d d i m . r a t i o , c h 7 o v p t h r e s h o l d 3 2 b i t s m e m o r y s w 4 c o n t r o l v d d m s w o c h i p e n a b l e s e q u e n c e s e l e c t i o n e n c p c n v n e g r t c + o s c + r e s e t @ 1 . 9 v v d d m b a t g n d v d d m c 3 2 k v r e f & d a c ( w / d v s ) v r e f & d a c ( w / d v s ) c h a r g e p u m p f o r s w v o u t 1 v n e g i 2 c c o n t r o l i n t e r f a c e ( f a s t m o d e u p t o 4 0 0 k b / s ) v d d m s c l s d a b o d y d i o d e c o n t r o l b a t v o u t 1 s e q p l l s y n c f l o a t i n g g n d s e l e c t i o n a 9 . b i t 0 c h 1 0 p f m o r l v c - m o d e s y n c . s t e p - d o w n + - l x 1 0 p v d d 4 / 1 0 v d d m v o u t 1 0 / f b 1 0 v r e f & d a c ( w / d v s ) v n e g r e g . p f m 1 0 v o u t 1 b a t b o d y d i o d e c o n t r o l m a x ( b a t , v o u t 1 ) r e s e t b a s e c o n t r o l l e r p o r / o s c / u v p / o v p / o c p / o t p v r e f & d a c ( w / d v s ) c h 7 ( w l e d ) h v c - m o d e a s y n c . s t e p - u p f o r 2 t o 6 w l e d v r e f & d a c + -
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5035a/b - 02 february 2017 6 operation the rt 5035a/b is a highly integrated dsc power management ic that contains 7 - ch switching dc - dc converters, two generic ldo, one keep alive low quiescent ldo, one load switch with soft - start control and current limit, one switch with reverse leakage prevention from backup battery, and a real - time clock (rtc) that includes a time counter and a 32768hz oscillator. ch1 : step - up dc - dc converter ch1 is a step - up converter for motor driver power in dsc system. the converter operates at asynchronous pfm or fixed frequency pwm current mode which can be set by the i 2 c interface. ch2 : synchronous step - up / down dc - dc converter ch2 is a synchronous step - up / down converter for system i/o power. the converter operates at fixed frequency pwm current mode. ch3 : synchronous step - down dc - dc converter ch3 is suitable for core power in dsc system. the converter operates in fixed frequency pwm mode with integrated internal mosfets, fb resistors and compensation network. t he ch3 also can be adjust ed output voltage if i 2 c is set to use the external resistor. ch4 : synchronous step - down dc - dc converter ch4 is suitable for memory power in dsc system. the converter operates in fixed frequency pwm mode with integrated internal mosfets, fb resistors and compensation network. ch5 : synchronous step - down dc - dc conver ter the converter operates in fixed frequency pwm mode with integrated internal mosfets, fb resistors and compensation network. t he ch 5 also can be adjust ed output voltage if i 2 c is set to use the external resistor. ch6 : generic ldo ch6 is a generic low voltage ldo for multiple purpose power. ch7 : wled driver ch7 is a wled driver that can support 6wled/30ma, and it can setting ovp threshold, dimming current level and power on/off by i 2 c interface. ch8 : generic ldo ch8 is a generic low voltage ldo for mu ltiple purpose power. ch9 : keep alive ldo and rtc the rt 5035a/b provides a 3.1v output ldo for all ic control circuits and real time clock. vneg charge pump the charge pump is to increase the vgs driving of big p - mosfet in ch2/3/4/ 5/10 . when bat < 3.6v and one of ch2/3/4/ 5/10 turns on, vneg charge pump will turn on and start to pump. load switch (sw4) the load switch is equipped with soft - start inrush control and current limit function (sw4). ch 10 : synchronous step - down dc - dc converter ch 10 is suitable for memory power in dsc system. the converter operates at asynchronous pfm or fixed frequency pwm current mode which can be set by the i 2 c interface and it integrated internal mosfets, fb resistors and compensation network. t he ch10 also can be adjust ed output voltage if i 2 c is set to use the external resistor.
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5035a/b - 02 february 2017 www.richtek.com 7 absolute maximum ratings (note 1) ? supply voltage : bat, pvdd2, pvdd3, pvdd4/10, pvdd5, pvdd6, pvdd8, swi ----------- ?? 0.3v to 6v ? power switch : lx1,lx2a, lx2b, lx3, lx4, lx5, lx10, cp -------------------------------- ---------- ?? 0.3v to 6v ? power switch : lx7 -------------------------------- -------------------------------- ------------------------------- ?? 0.3v to 24v ? output node : vout1 to vout6, swo, vout8, vout10, rtcpwr, vddm ------------------- ?? 0.3v to 6v ? output node : cn, vneg -------------------------------- -------------------------------- --------------------- ? (bat ? 6v) to 0.3v ? other pins -------------------------------- -------------------------------- -------------------------------- ---------- ?? 0.3v to 6v ? power dissipation, p d @ t a = 25 ? c wqfn - 40l 5x5 -------------------------------- -------------------------------- -------------------------------- ---- ? 3.6 3 w ? package thermal resistance (note 2) wqfn - 40l 5x5, ? ja -------------------------------- -------------------------------- ------------------------------ ? 27.5 ? c/w wqfn - 40l 5x5, ? j c -------------------------------- -------------------------------- ------------------------------ ? 6 ? c/w ? junction temperature -------------------------------- -------------------------------- ---------------------------- ? 150 ? c ? lead temperature (soldering, 10 sec.) -------------------------------- -------------------------------- ------ ? 260 ? c ? storage temperature range -------------------------------- -------------------------------- ------------------- ? ? 65 ? c to 125 ? c ? esd susceptibility (note 3) hbm (human body model) -------------------------------- -------------------------------- -------------------- ? 2kv mm (machine model) -------------------------------- -------------------------------- --------------------------- ? 200v recommended operating conditions (note 4 ) ? supply voltage : bat -------------------------------- -------------------------------- ---------------------------- ? 1.8v to 5.5v ? ambient temperature range -------------------------------- -------------------------------- ------------------ ? ? 40 ? c to 85 ? c ? junction temperature range -------------------------------- -------------------------------- ----------------- ? ? 40 ? c to 125 ? c electrical characteristics (vddm = 3. 1 v, t a = 25 ? c, unless otherwise specified) parameter symbol test condition s min typ max unit supply voltage vddm over voltage protection v ddm rising 5.8 6 6.2 v vddm over voltage protection hysteresis -- 0.25 -- v bat uvlo high threshold voltage (for li) (part. a) v bat rising -- 2.6 2.678 v bat uvlo low threshold voltage (for li) (part. a) 2.328 2.4 -- v bat uvlo high threshold voltage (for 2aa) (part. b) v bat rising -- 1.7 1.751 v bat uvlo low threshold voltage (for 2aa) (part. b) 1.455 1.5 -- v
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5035a/b - 02 february 2017 8 parameter symbol test condition s min typ max unit supply current shutdown supply current into bat ( including ch9 keep - alive ldo) i off,bat en = 0v, reg.shdn_en1 = 0, reg.shdn_en10 = 0 and vout1 = 0v, bat = 3.3v -- 10 -- ? a shutdown supply current into bat ( including ch9 keep - alive ldo) i off,bat en = 0v, reg.shdn_en1 = 0, reg.shdn_en10 = 1 and vout1 = 0v, bat = 3.3v a nd ch10 no - switching -- -- 80 ? a shutdown supply current into vout1 ( including ch9 keep - alive ldo) i off,vout1 en = 0v, reg.shdn_en1 = 1, reg.shdn_en10 = 0 and ch1 no - switching and vout1 = 4.2v, bat = 3.3v -- -- 80 ? a shutdown supply current into vout1 (including ch9 keep - alive ldo) i off,vout1 en = 0v, reg.shdn_en1 = 1, reg.shdn_en10 = 1 and ch1 no - switching and vout1 = 4.2v, bat = 3.3v -- -- 100 ? a ch1 (sync step - up pwm) + ch2 (sync step - up/down) + ch3 (sync step - down) + ch4 (sync step - down) + ch10 (sync step - down) supply current into vddm i q1234,10 en = 3.3v, reg.shdn_en1 = 1, a nd non switching. -- -- 1600 ? a ch2 (sync step - up/down) + ch3 (sync step - down) + ch4 (sync step - down) + ch10 (sync step - down) supply current into vddm i q234,10 en = 3.3v, a nd non switching. -- -- 1400 ? a ch5 (sync step - down) supply current into vddm i q5 en = 3.3v, a nd non switching -- -- 400 ? a ch6 (ldo) supply current into vddm i q6 en = 3.3v, a nd no load. -- -- 100 ? a ch7 (wled) in async step - up mode supply current into vddm i q7bo en = 3.3v, a nd non switching -- -- 500 ? a ch8 (ldo) supply current into vddm i q8 en = 3.3v, a nd no load. -- -- 100 ? a ch10 (sync step - down) supply current into vddm i q10 en = 3.3v , and non switching, -- -- 400 ? a oscillator ch1, 3, 4, 5, 10 operation frequency f osc ch1 in pwm mode 1800 2000 2200 k hz ch2, 7 operation frequency f osc 900 1000 1100 k hz ch1 maximum duty cycle (step - up) f osc = 2000 k hz 80 83 86 % ch2 maximum duty cycle at lx2b f osc = 1000 k hz 80 83 86 % ch2 maximum duty cycle at lx2a -- -- 100 %
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5035a/b - 02 february 2017 www.richtek.com 9 parameter symbol test condition s min typ max unit ch3 maximum duty cycle (step - down) -- -- 100 % ch4 maximum duty cycle (step - down) -- -- 100 % ch5 maximum duty cycle (step - down) -- -- 100 % ch7 maximum duty cycle (wled) step - up mode 91 93 97 % ch10 maximum duty cycle (step - down) -- -- 100 % feedback and output regulation voltage vout1 accuracy a1.vout1 = 0 to 7 ? 1.5 -- 1.5 % a1.vout1 = 8 to 15 ? 2 -- 2 % vout2, 3 , 10 accuracy t he voutx typical values are listed next. ? 1.5 -- 1.5 % vout4 accuracy a2.vout4 = 0 to 3 (near 1.8v) ? 1.5 -- 1.5 % a2.vout4 = 4 to 7 (near 1.5v) ? 2 -- 2 % vout5 accuracy a2.vout5 = 0 to 3 ? 1.5 -- 1.5 % a2.vout5 = 4 to 7 ? 2 -- 2 % vout6 accuracy a3.vout6 = 0 to 8 ? 2 -- 2 % a3.vout6 = 9 to 15 ? 2 -- 2 % vout8 accuracy a4.vout8 = 0 to 3 ? 2 -- 2 % a4.vout8 = 4 to 7 ? 2 -- 2 % feedback regulation voltage @ fb7 0.285 0.3 0.315 v vddm voltage (ch9 ldo output regulation) 3.01 3.1 3.19 v power switch ron and current limit ch1 on resistance of mosfet r ds(on)_1 p - mosfet, vout1 = 3.3v -- 150 200 m ? n - mosfet, vout1 = 3.3v -- 100 150 m ? ch1 current limitation (step - up) i lim_1 2.5 3.5 4.5 a ch2 on resistance of mosfet r ds(on)_2a p ? mosfet (pvdd2 ?? lx2a), pvdd2 = vout2 = 3.3v -- 100 150 m ? n ? mosfet (lx2a ? gnd), pvdd2 = vout2 = 3.3v -- 200 300 m ? ch2 on resistance of mosfet r ds(on)_2b p ? mosfet (lx2b ? vout2), pvdd2 = vout2 = 3.3v -- 150 200 m ? n ? mosfet (lx2b ? gnd), pvdd2 = vout2 = 3.3v -- 100 150 m ? ch2 current limitation i lim_2 b oth pmos (pvdd2 ? lx2a) and nmos (lx2b ? ? gnd) 2.2 3 4 a
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5035a/b - 02 february 2017 10 parameter symbol test condition s min typ max unit ch3 on resistance of mosfet r ds(on)_3 p ? mosfet, pvdd3 = 3.3v -- 200 300 m ? n - mosfet, pvdd3 = 3.3v -- 150 220 m ? ch3 current limitation (step - down) i lim_3 2.2 3 3.8 a ch4 on resistance of mosfet r ds(on)_4 p - mosfet, pvdd4 = 3.3v -- 350 400 m ? n - mosfet, pvdd4 = 3.3v -- 350 400 m ? ch4 current limitation (step - down) i lim_4 1 1.5 2 a ch5 on resistance of mosfet r ds(on)_5 p - mosfet, pvdd5 = 3.3v -- 350 400 m ? n - mosfet, pvdd5 = 3.3v -- 350 400 m ? ch5 current limitation (step - down) i lim_5 1 1.5 2 a ch7 on resistance of mosfet r ds(on)_7 n - mosfet -- 400 500 m ? ch7 current limitation i lim_7 n - mosfet 0.6 0.8 1 a ch10 on resistance of mosfet r ds(on)_10 p - mosfet, pvdd10 = 3.3v -- 350 400 m ? n - mosfet, pvdd10 = 3.3v -- 350 400 m ? ch10 current limitation (step - down) i lim_10 1 1.5 2 a sw4 load switch supply voltage of sw4 at swi swi 1.2 3.6 v sw4 on resistance of mosfet r ds(on) _sw4 swi = 1.8v, v out1 = 3.6v, i o = 400ma -- 100 130 m ? swi = 3.6v, v out1 = 5v, i o = 400ma -- 100 130 m ? sw4 soft - start time from enabled to v swo = v swi = 1.8v -- 1.4 -- ms current limit of sw4 i lim_sw4 swi = 1.8v 500 900 -- ma ch6 ldo supply voltage of ch6 pvdd6 2.7 -- 5.5 v psrr+ of ch6 1 k hz, i o = 10ma, pvdd6 = 3.6v, vout6 = 2.7v -- ? 60 -- db ch6 dropout voltage vout6 = 2.7v, i o = 100ma -- 50 80 mv current limit of ch6 i lim_6 vout6 = 2.7v 300 450 600 ma control cp pull down resistance 70 100 ? k ? en input high level threshold 1.3 -- -- v en input low level threshold -- -- 0.4 v en sink current -- 1 3 ? a sync input high level threshold 1.3 -- -- v sync input low level threshold -- -- 0.4 v
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5035a/b - 02 february 2017 www.richtek.com 11 parameter symbol test condition s min typ max unit sync sink current -- 1 3 ? a thermal protection thermal shutdown t sd 125 160 -- c thermal shutdown hysteresis ? t sd -- 20 -- c vneg charge pump charge pump low threshold to start nvst m onitor bat falling 3.4 3.6 3.8 v charge pump hysteresis gap to stop ? nvst 0.1 0.2 0.3 v (bat - vneg) clamp level 4.1 4.5 4.9 v ch8 ldo supply voltage of ch8 pvdd8 2.7 -- 5.5 v psrr+ of ch8 1khz, i o = 10ma, pvdd8 = 3.6v, vout8 = 3.4v -- ? 60 -- db ch8 dropout voltage vout8 = 3.4v, i o = 100ma -- 40 60 mv current limit of ch8 i lim_ 8 vout8 = 3.4v 220 300 380 ma ch9 keep - alive ldo supply voltage of ch9 at vout1 pin 2.4 -- 5.5 v psrr+ of ch9 1khz, i o = 1ma, v ddm = 3.1v -- ? 40 -- db ch9 dropout voltage v ddm = 3.1v, i o = 20ma -- 220 300 mv current limit of rtc ldo i lim _9 v ddm = 3.1v 50 100 -- ma hysteresis low f alling 2.15 2.2 -- v hysteresis high r ising -- 2.4 2.45 v rising delay time -- -- 0.5 s ch9 quiescent current e xcluding rtc quiescent current -- 10 -- ? a rtc rtc operation voltage 1. 9 -- 3.3 v rtc quiescent current ( i ncluding rtc_uvlo, rtc_osc, and time counter) rtcpwr > uvlo t hreshold xin = xout = 14pf -- -- 3 ? a rtcpwr < uvlo t hreshold -- -- 0.2 ? a rtc clock -- 32.768 -- khz rtc clock accuracy rtcpwr = 1. 9 v to 3.3v ? 10 -- 10 ppm rtc clock output high p in c32k s ource out 0.1ma vddm ?? 0.3 -- -- v rtc clock output low p in c32k s ink 0.1ma -- -- 0.3 v reset
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5035a/b - 02 february 2017 12 parameter symbol test condition s min typ max unit rtc under voltage lockout threshold (uvlo) v rtc_f rtcpwr f alling 1.8 1.9 2 v v rtc_r rtcpwr r ising v rtc_f + 20m 2.2 2.3 v rtc o sc startup time -- 0.5 1 s switch ron from vddm to rtcpwr p - mosfet, v ddm = 3.1v -- 60 -- ? under - voltage and over - voltage protection ch1 ovp threshold @ vout1 5.6 5.8 6 v ch2 ovp threshold @ vout2 5.8 6 6.2 v ch7 ovp threshold accuracy @ lx7 target voltage is the chosen one in a7.ovp7 target ? ? 1 target target + 1 v ch1 uvp threshold @ vout1 1.95 2.25 2.55 v ch2 uvp threshold @ vout2 1.4 1.6 1.8 v ch3 uvp threshold @ vout3 0.525 0.6 0.675 v ch4 uvp threshold @ vout4 0.7 0.8 0.9 v sw4 load switch uvp threshold vswi - vswo -- 0.9 -- v sw4 load switch uvp threshold vswo -- 0.9 -- v ch5 uvp threshold @ vout5 0.7 0.8 0.9 v ch6 uvp threshold @ vout6 a3.vout6 = 0 to 9 -- 1.6 -- v a3.vout6 = 10 to 15 -- 0.8 -- ch8 uvp threshold @ vout8 target voltage is the chosen one in a4.vout8 -- 0.5 x target -- v ch10 uvp threshold @ vout10 0.7 0.8 0.9 v ch1 over - load p threshold (olp) @ vout1 target voltage is the chosen one in a1.vout1 -- target ? ? 0.6 -- v ch2 olp threshold @ vout2 target voltage is the chosen one in a1.vout2 -- target ? ? 0.4 -- v ch3 olp threshold @ vout3 target voltage is the chosen one in a2.vout3 -- target ? ? 0.15 -- v ch4 olp threshold @ vout4 target voltage is the chosen one in a2.vout4 -- target ? ? 0.2 -- v ch5 olp threshold @ vout5 target voltage is the chosen one in a3.vout5 -- target ? ? 0.2 -- v ch10 olp threshold @ vout10 target voltage is the chosen one in a5.vout10 -- target ? 0.2 -- v protection delay time for ocp and olp, except ocp of ch2 -- 100 -- ms i 2 c sda, sclk input high level threshold 0.7 x vddm -- -- v sda, sclk input low level threshold -- -- 0.3 x vddm v
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5035a/b - 02 february 2017 www.richtek.com 13 parameter symbol test condition s min typ max unit sclk clock rate f scl vddm = 3.1v, vout2 = 3.3v -- -- 400 khz hold time (repeated) start condition. after this period, the first clock pulse is generated t hd;sta 0.6 -- -- ? s low period of the scl clock t low 1.3 -- -- ? s high period of the scl clock t high 0.6 -- -- ? s set - up time for a repeated start condition t su;sta 0.6 -- -- ? s data hold time t hd;dat 0 -- 0.9 ? s data set - up time t su;dat 100 -- -- ns set - up time for stop condition t su;sto 0.6 -- -- ? s bus free time between a stop and start condition t buf 1.3 -- -- ? s rise time of both sda and scl signals t r 20 -- 300 ns fall time of both sda and scl signals t f 20 -- 300 ns sda and scl output low sink current i ol sda or scl v oltage = 0.4v 2 -- -- ma output voltage ramp rate vout1 ramp rate v out1 = 3.6v to 5.3v -- 1.24 -- v/ms vout 2 ramp rate v out 2 = 0 v to 3.25 v -- 0.82 -- v/ms vout 3 ramp rate v out 3 = 0 v to 1.1 v -- 0.33 -- v/ms vout 4 ramp rate v out 4 = 0 v to 1.8 v -- 0.44 -- v/ms vout 5 ramp rate v out 5 = 0 v to 2.2 v -- 0.6 -- v/ms vout 6 ramp rate v out 6 = 0 v to 2.7 v -- 0.84 -- v/ms vout 8 ramp rate v out 8 = 0 v to 3.4 v -- 0.84 -- v/ms vout 10 ramp rate v out 10 = 0 v to 1.35 v -- 0.41 -- v/ms ramp rate accuracy of all the above ? 40 -- + 40 % enabling delay time delay time step resolution for endly2, 3, 4, 10 1.5 2 2.5 ms off discharge vout 1, 2, 3, 4, 5, 10 discharge equivalent resistance v ddm = 3. 1 v and v outx = 1v 50 -- -- ? sw4 discharge equivalent resistance v ddm = 3. 1 v and swo = 1v 4 00 -- -- ? vout6 discharge equivalent resistance v ddm = 3. 1 v and v out6 = 1v 200 -- -- ? vout8 discharge equivalent resistance v ddm = 3. 1 v and v out8 = 1v 200 -- -- ?
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5035a/b - 02 february 2017 14 parameter symbol test condition s min typ max unit vddm discharge equivalent resistance v m = 4.2v and v ddm = 1v 200 -- -- ? each channel discharge finish threshold for next channel starting to turn off 0.05 0.1 0.15 v ch1 async. pfm n - mosfet on - time -- 0.5 -- ? s minimum off - time -- 0.5 -- ? s n - mosfet current limit -- 0.8 -- a vout1 regulation voltage 3.5 3.6 3.7 v note 1. stresses beyond those listed absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of t he specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ? ja is measured at t a = 25 ? c on a high effective thermal conductivity four - layer test board per jedec 51 - 7. ? jc is measured at the exposed pad o f the package. note 3. devices are esd sensitive. handling precaution recommended. note 4. the device is not guaranteed to function outside its operating conditions.
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5035a/b - 02 february 2017 www.richtek.com 15 typical application circuit r t 5 0 3 5 a / b 3 f b 7 r e x t 1 0 v d d m 3 8 b a t l x 5 2 5 1 3 l 5 2 . 2 h c o u t 5 1 0 f p v d d 6 v o u t 6 v b a t c b a t 4 . 7 f l x 7 6 v b a t v o u t 8 2 8 p v d d 8 2 9 b a c k l i g h t v m o t o r v d d m t o a s i c p o w e r s e q u e n c e r 2 t o a s i c p o w e r s e q u e n c e r r t c p w r 3 7 r r t c p w r 1 k + c 3 2 k 3 1 t o a s i c p o w e r s e q u e n c e r b a c k u p b a t t e r y x i n 3 6 x o u t 3 5 g n d 4 1 ( e x p o s e d p a d ) r t c g n d 3 4 l x 2 a 2 3 2 1 p v d d 2 2 4 l x 2 b l 2 2 . 2 h v b a t c i n 2 1 0 f s c l 1 8 l x 4 7 l 4 2 . 2 h c o u t 4 1 0 f v o u t 4 / s w i 1 4 c i n 4 4 . 7 f 8 p v d d 4 / 1 0 v b a t p v d d 3 3 2 3 3 l x 3 3 0 v o u t 3 / f b 3 l 3 1 . 2 h c i n 3 1 0 f v b a t c o u t 3 4 0 f v n e g 1 0 c v n e g 1 f v o u t 2 c o u t 2 1 0 f x 2 1 9 1 7 s d a v i / o 3 . 2 5 v i 2 c b u s c p c n 1 2 1 1 c c p 1 0 n f e n c h i p e n a b l e 2 2 f r o m a s i c p o w e r s e q u e n c e r c x i n c x o u t r s d a r s c l c i n 7 1 f l 7 1 0 h c i n 8 1 f c o u t 8 2 . 2 f c v d d m 2 . 2 f c r t c p w r 1 f y 1 c s w o 1 0 f 1 6 s w o v o u t 5 / f b 5 2 7 p v d d 5 2 6 v b a t c i n 5 4 . 7 f 5 c i n 6 1 f 4 c o u t 6 2 . 2 f 1 5 p f 1 5 p f l x 1 1 l 1 2 . 2 h v b a t c i n 1 4 . 7 f v m o t o r v o u t 1 4 0 c o u t 1 1 0 f x 2 v o u t 2 v o u t 3 v o u t 4 s w o s y n c 3 9 s e q 2 0 v o u t 5 v m o t o r v o u t 6 c o u t 7 1 f v o u t 8 l x 1 0 9 l 1 0 2 . 2 h c o u t 1 0 1 0 f v o u t 1 0 / f b 1 0 1 5 v o u t 1 0 d 7 d 1 d 2 d 3 d 4 d 5 d 6 r r e s e t 1 0 k v d d m r e s e t r s e q r 6 5 k
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5035a/b - 02 february 2017 16 typical operating characteristics ch1 boost efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 10000 output current (ma) efficiency(%) v out = 5v, l = 2.2h, c out = 10f x 2 v in = 1.8v v in = 2.4v v in = 3v v in = 3.6v v in = 4.2v v in = 4.5v ch2 buck-boost efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 output current (ma) efficiency(%) v out = 3.25v, l = 2.2h, c out = 10f x 2 v in = 1.8v v in = 2.4v v in = 3v v in = 3.6v v in = 4.2v v in = 5v ch3 buck efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 10000 output current (ma) efficiency (%) v out = 1.16v, l = 1.2h, c out = 44f v in = 1.8v v in = 2.4v v in = 3v v in = 3.6v v in = 4.2v v in = 5v ch4 buck efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 output current (ma) efficiency (%) v out = 1.8v, l = 2.2h, c out = 10f v in = 2.1v v in = 2.4v v in = 3v v in = 3.6v v in = 4.2v v in = 5v ch5 buck efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 output current (ma) efficiency (%) v out = 1.23v, l = 2.2h, c out = 10f v in = 1.8v v in = 2.4v v in = 3v v in = 3.6v v in = 4.2v v in = 5v ch7 efficiency vs. input voltage 0 10 20 30 40 50 60 70 80 90 100 1.8 2.1 2.4 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 input voltage (v) efficiency (%) load = 6wleds/30ma, l = 10h, c out = 1f
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5035a/b - 02 february 2017 www.richtek.com 17 ch10 buck efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 output current (ma) efficiency (%) v out = 1.35v, l = 2.2h, c out = 10f v in = 1.8v v in = 2.4v v in = 3v v in = 3.6v v in = 4.2v v in = 5v ch1 boost output voltage vs. output current 4.86 4.88 4.90 4.92 4.94 4.96 4.98 5.00 5.02 5.04 5.06 0 200 400 600 800 1000 1200 output current (ma) output voltage (v) l = 2.2h, c out = 10f x 2 v in = 1.8v v in = 2.4v v in = 3v v in = 3.6v v in = 4.2v v in = 4.5v ch2 buck-boost output voltage vs. output current 3.05 3.10 3.15 3.20 3.25 3.30 0 200 400 600 800 1000 output current (ma) output voltage (v) l = 2.2h, c out = 10f x 2 v in = 1.8v v in = 2.4v v in = 3v v in = 3.6v v in = 4.2v v in = 5v ch3 buck output voltage vs. output current 1.06 1.08 1.10 1.12 1.14 1.16 1.18 0 500 1000 1500 2000 output current (ma) output voltage (v) l = 1.2h, c out = 44f v in = 1.8v v in = 2.4v v in = 3v v in = 3.6v v in = 4.2v v in = 5v ch4 buck output voltage vs. output current 1.71 1.72 1.73 1.74 1.75 1.76 1.77 1.78 1.79 1.80 1.81 0 200 400 600 800 1000 output current (ma) output voltage (v) l = 2.2h, c out = 10f v in = 2.1v v in = 2.4v v in = 3v v in = 3.6v v in = 4.2v v in = 5v ch5 buck output voltage vs. output current 1.220 1.225 1.230 1.235 1.240 0 200 400 600 800 1000 output current (ma) output voltage (v) l = 2.2h, c out = 10f v in = 4.2v v in = 5v v in = 1.8v v in = 2.4v v in = 3v v in = 3.6v
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5035a/b - 02 february 2017 18 ch6 ldo output voltage vs. output current 2.900 2.905 2.910 2.915 2.920 2.925 2.930 2.935 2.940 2.945 2.950 0 50 100 150 200 output current (ma) output voltage (v) c out = 1f v in = 3v v in = 3.3v v in = 3.6v v in = 4.2v v in = 4.5v v in = 5v ch8 ldo output voltage vs. output current 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 5.06 5.07 0 50 100 150 200 output current (ma) output voltage (v) c out = 1f v in = 5v v in = 5.1v v in = 5.2v v in = 5.3v v in = 5.4v v in = 5.5v ch9 ldo output voltage vs. output current 3.00 3.05 3.10 3.15 3.20 0 10 20 30 40 50 output current (ma) output voltage (v) c out = 1f v in = 3.3v v in = 3.6v v in = 3.9v v in = 4.2v v in = 4.5v v in = 5v ch10 buck output voltage vs. output current 1.320 1.325 1.330 1.335 1.340 1.345 1.350 1.355 0 200 400 600 800 1000 output current (ma) output voltage (v) v in = 1.8v v in = 2.4v v in = 3v v in = 3.6v v in = 4.2v v in = 5v l = 2.2h, c out = 10f ch7 output voltage vs. input voltage 18.0 18.2 18.4 18.6 18.8 19.0 19.2 19.4 19.6 19.8 1.8 2.1 2.4 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 5.7 input voltage (v) output voltage (v) load = 6wleds/30ma, l = 10h, c out = 1f ch7 led current vs. dimming level 0 5 10 15 20 25 30 35 0 4 8 12 16 20 24 28 32 dimming level i led (ma) v in = 1.8v v in = 3v v in = 5.5v load = 6wleds, c out = 1f
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5035a/b - 02 february 2017 www.richtek.com 19 ch6 ldo dropout voltage vs. load current 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0 50 100 150 200 load current (ma) dropout voltage (v) 25c 90c ? 40c ch8 ldo dropout voltage vs. load current 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0 50 100 150 200 load current (ma) dropout voltage (v) 25c 90c ? 40c ch9 ldo dropout voltage vs. load current 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 10 20 30 40 50 load current (ma) dropout voltage (v) 25c 90c ? 40c ch6 ldo psrr -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 100000 1000000 frequency (hz) psrr (db) pvdd6 = 3.6v, vout6 = 2.7v, i out = 10ma ch8 ldo psrr -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 100000 1000000 frequency (hz) psrr (db) pvdd8 = 3.6v, vout8 = 3.4v, i out = 10ma ch9 ldo psrr -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 100000 1000000 frequency (hz) psrr (db) vddm = 3.1v, i out = 1ma
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5035a/b - 02 february 2017 20 application information ch1 : step - up dc - dc converter ch1 is a step - up converter for motor driver power in dsc system. the converter operates at a sync pfm or fixed frequency pwm current mode which can be set by i 2 c . the converter integrates internal mosfets, fb resistors, compensation network and synchronous rectifier for up to 95% efficiency. the output voltage of ch1 is adjustable by the i 2 c interface in the range of 3.6v to 5.3v. when ch1 operates at a sync . pfm mode, lx1 switches as below waveform : ch1 ovp operation usually, ch1 suffers bemf of motor, and ovp would occur abnormally. to eliminate this, the operation of ch1 is as follows. when ovp (5.8v) occurs, ch1 stops switching and ch1 discharges vout1 through internal mos (only for discharge, i~ 30ma) until ovp hysteresis (5.5 v) low threshold. if there is longer bemf, th e charging and discharging period will repeat. pmu itself doesn t shut down immediately, but shuts down when continuous 100ms ovp occurs. ch2 : synchronous step - up / d own dc - dc converter ch2 is a synchronous step - up / down converter for system i/o power. the converter operates at fixed frequency pwm current mode. the converter integrates internal mosfets, fb resistors, compensation network and synchronous rectifier for up to 95% efficiency. the output voltage of ch2 can be adjusted by the i 2 c interface in the range of 2.9 v to 3. 6 5v. v l x 1 i l 1 i l p k t o n = c o n s t a n t o n t i m e t o n l e t i l 1 i n c r e a s e t o i l p k t o f f 3 m i n o f f t i m e n e x t c y c l e a c t i v a t e d b y e a ( i f v o u t 1 < 3 . 6 v ) e a m o n i t o r v o u t 1 3 3 . 6 v t o a c t i v a t e t h e s w i t c h i n g . i f v i n ( b a t ) - v f > 3 . 6 v a s y n c b o o s t n o t s w i t c h . i f v i n - v f < 3 . 6 v , l x 1 s w i t c h a s t h e a b o v e w a v e f o r m . m a x i o u t w o u l d b e l i m i t e d b y p e a k c u r r e n t l i m i t a n d s w i t c h i n g f r e q u e n c y . ( w h e r e v f i s f o r w a r d v o l t a g e o f e x t e r n a l s c h o t t k y d i o d e . ) o u t p u t c h a r g e p e r c y c l e : q o = i l p k x i l p k x l / ( v o - v i ) / 2 = l x i l p k ^ 2 / 2 / ( v o - v i ) q o / c o u t d e t e r m i n e s t h e o u t p u t v o l t a g e r i p p l e . i o u t = q o x ( s w i t c h i n g f r e q u e n c y ) b e m f l o n g e r b e m f 3 0 m a 5 v 5 . 5 v 5 . 8 v i _ d i s c h a r g e 0 v o v p h i g h t h r e s h o l d = 5 . 8 v o v p h y s t e r e s i s l o w t h r e s h o l d = 5 . 5 v
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5035a/b - 02 february 2017 www.richtek.com 21 vneg charge pump t h e charge pump is to increase the vgs driving of big pmos in ch2/3/4/5/10. when bat < 3.6v and one of ch2/3/4/5/10 turns on, vneg charge pump would turn on and start to pump. but when pumping, the bat threshold to turn off and stop charge pump becomes 3.9v. when pumping, the (bat ? vneg) voltage would be clamped at 4.5v. but because of charge pumping architecture limitation, most negative level of the vneg is only ( ? bat). hence, if bat < 4.5 / 2 = 2.25v, vneg is limited to ( ? bat). when vneg charge pump is off, vneg is connected internally to gnd. ch3 : synchronous step - dow n dc - dc converter ch3 is suitable for core power in dsc system. the converter operates in fixed frequency pwm mode with integrated mosfets, fb resistors and compensation network. the ch3 step - down converter can be o perated at 100% maximum duty cycle to extend battery o perating voltage range. the output voltage of ch3 is adjustable by the i 2 c interface in the range of 1v to 1.3v. besides, the ch3 also can be adjusted output voltage if i 2 c is set to use the external resistor. the vout can be calculated by the equation as below : v out_ch3 = (1 + r1 / r2) x v fb3 w here v fb3 is 0.8v typically and suggested value for r 1 is 100k ? to 600k ? . ch4 : synchronous step - down dc - dc converter ch4 is suitable for digital i/o power in dsc system. the converter operates in fixed frequency pwm mode with integrated internal mosfets, fb resistors and compensation network. the ch4 step - down converter can be operate d at 100% maximum duty cycle to extend battery operating voltage range. the output voltage of ch4 is adjustable by the i 2 c interface in the range of 1.35v to 2.1 4v. ch5 : synchronous step - down dc - dc converter ch5 is suitable for cmos sensor power in dsc system. the converter operates in fixed frequency pwm mode with integrate d internal mosfets, fb resistors and compensation network. the ch5 step - down converter can be operated at 100% maximum duty cycle to extend battery operating voltage range. the output voltage of ch5 is adjustable by the i 2 c interface in the range of 1. 2 v to 2 v or set by external feedback resistors, as expressed in the following equation : v out_ch5 = (1 + r1 / r2) x v fb5 where v fb5 is 0.8v typically and suggested value for r 1 is 100k ? to 600k ? . ch6 : generic ldo ch6 is a generic low voltage ldo for multiple purpose power. the ch6 is a linear regulator, designed to be stable over the entire operating load range with the use of external ceramic capacitors. ch6 has an on/off control which can be set by i 2 c commands. the output voltage of ch6 is adjustable by th e i 2 c interface in the range of 1.2v to 3 v. ch7 : wled driver ch7 is a wled driver operate s at a synchronous step - up mode with an internal mosfet and internal compensation. t he led current is defined by fb7 voltage and the external resistor between fb7 and gnd. the fb7 regulation voltage can be set in 32 steps from 9.2 mv to 300 mv, typically, via i 2 c interface. the wled current can be set by the following equation : i led (ma) = [ 0. 3 v / r ext ] x (dim7 + 1) / 32 where r ext is the current sense resistor from fb7 to gnd and (dim7 + 1) / 32 ratio refers to i 2 c control register file. the 0. 3 v voltage is with 5% accuracy. the maximum i led is defined by 0 .3 v / r ext . ch8 : generic ldo ch8 is a generic low voltage ldo for multiple purpose power. the ch8 is a linear regulator, designed to be stable over the entire operating load range with the use of external ceramic capacitors. ch8 has an on/off control which can be set by i 2 c commands. the output voltage of ch8 is adjustable by the i 2 c interface in the range of 1.5v to 5.2 v.
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5035a/b - 02 february 2017 22 ch9 : keep alive ldo and rtc related function block the rt 5035a/b provides a 3.1v output ldo for all ic control circuits and real time clock. the ldo features low quiescent current ( 3 ? a) and high output voltage accuracy. this ldo is always on, even when the system is shut down. for better stability, it is recommended to connect a 1 ? f to the vddm pin. the rtcpwr switch avoids back charging from the rtcpwr node into the input node vddm. ch 10 : synchronous step - down dc - dc converter ch 10 is suitable for memory power in dsc system. the converter operates in fixed frequency pwm mode or pfm mode with integrated internal mosfets, fb resistors and compensation network . the ch 10 step - down converter can be operated at 100% maximum duty cycle to extend battery operating voltage range. the output voltage of ch 10 is adjustable by the i 2 c interface in the range of 1. 2 v to 1.52 v or set by external feedback resistors, as expr essed in the following equation : v out_ch 10 = (1 + r1 / r2) x v fb 10 w here v fb 10 is 0.8v typically and suggested value for r 1 is 100k ? to 600k ? . rtc_ c32k the frequency divider from 32768hz to 1hz would generate the below 1hz wave that with a little jitter but the 1hz average frequency can be finely tuned. r t c p w r + - + - v r e f v m v m 3 . 1 v v d d m = 3 . 1 v 3 % b a t u v l o v m l o w b a t d i s c h a r g e u v l o 2 . 4 v / 2 . 2 v v d d m / r e s e t 2 . 6 v / 2 . 4 v + - b a t v m f a l l i n g d e l a y 4 m s c l = 4 0 m a ( m i n ) t o a s i c p o w e r s e q u e n c e r t o a s i c p o w e r s e q u e n c e r r t c p w r r t c p w r + 1 f b a c k u p b a t t e r y r t c p w r r t c p w r r t c p w r r b i a s c 2 c 1 r 1 f r e q d i v i d e r 1 h z c l o c k c 3 2 k n = 0 t o 6 3 c o u n t y y / m m / d d , w e e k , h h : m m : s s w i t h l e a p y e a r c o r r e c t i o n i n t e r n a l b u s t o a s i c p o w e r s e q u e n c e r 3 2 7 6 8 h z x o u t x i n r t c g n d r t c u v l o 1 . 9 v + - r t c p w r / r / r / e n v d d m r t c p w r r t c p w r r b i a s c 2 c 1 r 1 f r e q d i v i d e r 1 h z c l o c k 3 2 7 6 7 c l k o c 3 2 k 3 2 7 6 7 c l k o 3 2 7 6 7 c l k o n c l k o . . . 1 2 6 0 1 6 0 s e c n = 0 t o 1 2 7 f i n e t u n e 1 h z b y d i g i t a l d i v i d e r c a n c r e a t e t u n i n g r a n g e = ( - 6 0 t o 6 7 ) / ( 3 2 7 6 8 h z x 6 0 s ) = - 3 0 t o 3 3 p p m e a c h t u n e s t e p s i z e = 0 . 5 p p m . b u t t h e 1 h z w o u l d i n c l u d e j i t t e r a n d t h e c 3 2 k s t i l l i s n o t t u n e d . 1 h z c l o c k
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5035a/b - 02 february 2017 www.richtek.com 23 rtc time read/write method : when reading rtc time via i 2 c interface, suggest read 6 bytes (address a11 to a16) together and finish reading within 0.5 second to avoid the secon d carry issue. a 16.rtct_sec[0] can be used for checking whether second is carried during reading time. when writing rtc time via i 2 c interface, suggest to write 6 bytes (address a11 to a16) together. a11 is first and the n a12, a13, a14, a15, a16. suggest finishing writing within 0.5 second to avoid second carry issue during writing. output voltage ramp rate for instance, ch3 v core output voltage ramp up rate = 1.5 x 0.8v / 4 ms = 0.3 v/ms. t h e ramp up/down rate is kept the same for enabling soft - start or dynamic output voltage adjustment. each channel has different ramp rate as listed below. note : about dynamic voltage scaling, ch1, ch3, ch4, ch8, ch10 output voltage can be changed with out inrush and vout ramping control when they have been turned on (said, dynamically change vout). ch2, ch5, ch6 are not. synchronization and spread spectrum i f sync remains logic high or low, the spread spectrum clock will act the main clock for pwm. and, spread spectrum function can be turned off by register a15.ss. if the toggling clock of sync is detected, the pll clock will act the main clock for pwm and the clock of pll will track it s frequency. and the divis ion ratio is decided by a15.syn_div. furthermore, according to the logic high and low level threshold voltage , both 1.8v and 3v logic are compatible. if it isn't used, the s ync pin must be connected to gnd. if the clock of syn c is 12mhz, vddm is not recommended as pull - up power voltage. o ther power domains can be used if they fit the logic high and logic low threshold voltage. 3 . 7 m s 1 . 1 v 0 v 1 . 1 v 1 . 3 v r a m p r a t e = 1 . 5 x 0 . 8 v / 4 m s r a m p r a t e = 1 . 5 x 0 . 8 v / 4 m s 0 . 7 m s s p r e a d s p e c t r u m c l o c k g e n e r a t o r p l l d i v s y n c c l o c k f o r p w m s y n c h r o n i z a t i o n a 1 5 . s y n _ d i v 1 0 a 1 5 . s s c l k d e t e c t i o n a s i c v d d m t h e o u t p u t i n t e r f a c e o f a s i c : p u s h - p u l l i s p r e f e r r e d .
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5035a/b - 02 february 2017 2 4 power on/off sequence part.a : li (shdn_pfm1 = 0) e n p i n r e f _ g o o d v r e f , o s c , o t p , v d d m _ u v l o , s e q d e t e c t i o n a r e r e a d y . c h 3 c h 2 c h 4 v o u t 1 0 v 5 . 0 v ( f o r i n s t a n c e ) 0 v b a t b a t t e r y i n s t a l l e d a n d b a t u v l o g o e s l o w e n d l y 3 e n d l y 2 e n d l y 4 c h 1 0 e n d l y 1 0 p w m o p e r a t i o n v d d m 0 v 3 . 1 o r b a t 3 . 1 v v m ( i n t e r n a l ) b a t 5 v 3 . 1 o r b a t a 1 3 . s h d n _ e n 1 0 = 0 / r e s e t v d d m > 2 . 4 v a n d r t c o s c s t a b l e ( s y n c w i t h c 3 2 k ) s h d l y 2 = 0 s h d l y 4 = 0 s h d l y 1 0 = 0 s h d l y 3 b a t
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5035a/b - 02 february 2017 www.richtek.com 25 part.b : 2aa (shdn_pfm1 = 1) ch1 : f or 2aa case, a s long as the bat voltage is higher than uvlo and en pin = l, ch1 keeps working in pfm mode 3.6v (default shdn_en1 = 1) . however, when a 14 .pwm1 = 1, en pin = h and the vddm voltage is higher than uvlo, ch1 will switch from pfm mode to pwm mode. as for li battery case, to save electricity, when bat voltage is higher than uvlo and en pin = l, the ch1 would be off and truly shutdown (default shdn_e n 1 = 0) ch2/3 /4 : ch2 , ch3 and ch4 are both enabled by en pin and with turn on delay time defined in i 2 c register a 9 to a10. c h 10 : ch10 is also equipped pfm operation to reduce operating quiescent current for memory self - refresh application. when en = h, i 2 c registers can be set to ready to get into standby mode. (set shdn_en1 = 1 and shdn_en10 = 1) e n p i n r e f _ g o o d v r e f , o s c , o t p , v d d m _ u v l o , s e q d e t e c t i o n a r e r e a d y . c h 3 c h 2 c h 4 v o u t 1 0 v 5 . 0 v ( f o r i n s t a n c e ) 0 v b a t b a t t e r y i n s t a l l e d a n d b a t u v l o g o e s l o w e n d l y 3 e n d l y 2 e n d l y 4 c h 1 0 e n d l y 1 0 p f m o p e r a t i o n p w m o p e r a t i o n v d d m 0 v 3 . 1 o r b a t 3 . 1 v 3 . 6 v p f m o p e r a t i o n v m ( i n t e r n a l ) 5 v a 1 3 . s h d n _ e n 1 0 = 0 / r e s e t v d d m > 2 . 4 v a n d r t c o s c s t a b l e ( s y n c w i t h c 3 2 k ) s h d l y 2 = 0 s h d l y 4 = 0 s h d l y 1 0 = 0 s h d l y 3 3 . 6 v 3 . 6 v 3 . 6 v
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5035a/b - 02 february 2017 26 and then en goes low , ic will get into standby mode with ch1 and ch10 operating in pfm mode. if bat > 2.8 v is guarantee d, shdn_en1 could be 0 to save electricity in standby mode. as for back to shutdown mode, en goes high , and to set i 2 c registers back to shutdown mode (shdn_en10 = 0 and shdn_en1 = 0 for li battery. shdn_en10 = 0 and shdn_en1 keeps 1 for 2aa) and then en goes low finally. power sequence with delay time the s tart point refer r ed by endlyx delay time begins when the en pin goes high. for instance, a 1 4 .en8 = 1, ch8 turns on immediately. i 2 c register information the rt 5035a/b i 2 c interface power must be supplied by either vout2 or an equal potential node. if = low, i 2 c read/write can not function. the rt 5035a/b i 2 c slave address = 0011000 (7bits). i 2 c interface supports fast mode (bit rate up to 400kb/s). the write or read bit stream (n 3 ? 1) is shown below : e n p i n a 7 . e n 8 c h 8 v o u t reset s d a s c l t f t l o w t h d ; s t a t h d ; d a t t h i g h t s u ; d a t t s u ; s t a t h d ; s t a t s p t b u f t s u ; s t o p s t r s r s t f t r s 0 1 a p l s b m s b a a s s u m e a d d r e s s = m d a t a f o r a d d r e s s = m d a t a f o r a d d r e s s = m + n - 1 a d a t a f o r a d d r e s s = m + 1 s 0 p a s s u m e a d d r e s s = m d a t a f o r a d d r e s s = m d a t a f o r a d d r e s s = m + n - 1 d a t a f o r a d d r e s s = m + 1 s r s l a v e a d d r e s s r e g i s t e r a d d r e s s s l a v e a d d r e s s d a t a 1 r / w r / w d a t a n l s b m s b a a a a a a a a r e a d n b y t e s f r o m r t 5 0 3 5 l s b m s b d a t a 2 d a t a n l s b m s b l s b s l a v e a d d r e s s r e g i s t e r a d d r e s s d a t a 1 d a t a 2 m s b m s b l s b w r i t e n b y t e s t o r t 5 0 3 5 d r i v e n b y m a s t e r , d r i v e n b y s l a v e ( r t 5 0 3 5 ) , s t a r t , r e p e a t s t a r t s t o p , s s r p
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5035a/b - 02 february 2017 www.richtek.com 27 i 2 c register file address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a1 0x01 meaning vout1 vout2 default 1 1 1 1 1 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b b b b b b b b vout1 setting of ch1 output voltage (range : 5.3v to 3.6v, default = 3.6v) code voltage code voltage code voltage code voltage 0000 5.3v 0100 4.9v 1000 4.5v 1100 4v 0001 5.2v 0101 4.8v 1001 4.4v 1101 3.9v 0010 5.1v 0110 4.7v 1010 4.3v 1110 3.8v 0011 5v 0111 4.6v 1011 4.2v 1111 3.6v vout2 setting of ch2 output voltage (range : 3.65v to 2.9v, default = 3.25v) code voltage code voltage code voltage code voltage 0000 3.65v 0100 3.45v 1000 3.25v 1100 3.05v 0001 3.6v 0101 3.4v 1001 3.2v 1101 3v 0010 3.55v 0110 3.35v 1010 3.15v 1110 2.95v 0011 3.5v 0111 3.3v 1011 3.1v 1111 2.9v note : if ch1 operate in pfm mode (the bit a 14 .pwm1 = 0), vout1 = 3.6v only address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a2 0x02 meaning vout3 vout4 default decided by seq decided by seq read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b b b b b b b b vout3 setting of ch3 out put voltage (range : 1.3v to 1 v, default is setting by seq ) code voltage code voltage code voltage code voltage 0000 1.3v 0100 1.22v 1000 1.14v 1100 1.04v 0001 1.28v 0101 1.2v 1001 1.12v 1101 1.02v 0010 1.26v 0110 1.18v 1010 1.1v 1110 1 v 0011 1.24v 0111 1.16v 1011 1.06v 1111 ref vout4 setting of ch4 output voltage (range : 2.14v to 1.35v, default is setting by seq ) code voltage code voltage code voltage code voltage 0000 2.14v 0100 2v 1000 1.84v 1100 1.5 v 0001 2.1 v 0101 1.96v 1001 1.8 v 1101 1.46v 0010 2.06v 0110 1.92v 1010 1.76v 1110 1.39v 0011 2.04v 0111 1.88v 1011 1.54v 1111 1.35v
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5035a/b - 02 february 2017 28 address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a3 0x03 meaning reserved vout5 vout6 default 0 1 1 0 0 0 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b b b b b b b b vout5 setting of ch5 output voltage (range : 2 v to 1.2v, default = 1.2 v) code voltage code voltage code voltage code voltage 000 2 v 010 1.5 v 100 1.26v 110 1.2 v 001 1.8 v 011 1.35 v 101 1.23v 111 ref vout6 setting of ch6 output voltage (range : 3v to 1.2v, default = 2.7v) code voltage code voltage code voltage code voltage 0000 3v 0100 2.6v 1000 2.2v 1100 1.7v 0001 2.9v 0101 2.5v 1001 2v 1101 1.5v 0010 2.8v 0110 2.4v 1010 1.9v 1110 1.4v 0011 2.7v 0111 2.3v 1011 1.8v 1111 1.2v address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a4 0x04 meaning vout8 dim7 default 0 1 0 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b b b b b b b b vout8 setting of ch8 output voltage (range : 5.2v to 1.5 v , default = 5v) code voltage code voltage code voltage code voltage 000 5.2v 010 5v 100 3.4v 110 3v 001 5.1v 011 3.5v 101 3.3v 111 1.5v dim7 defines led current dimming ratio of ch7 the dimming ratio is (dim7 + 1) / 32. dim7 define fb7 regulation voltage = 0. 3 v x (dim7 + 1) / 32 address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a5 0x05 meaning reserved reserved reserved reserved reserved vout10 default 0 0 0 0 0 by seq read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b b b b b b b b vout10 setting of ch10 output voltage (range : 1. 5 2v to 1. 2 v , default = seq setting) code voltage code voltage code voltage code voltage 000 1.52v 010 1.37v 100 1.25v 110 1.2v 001 1.5v 011 1.35v 101 1.22v 111 ref
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5035a/b - 02 february 2017 www.richtek.com 29 address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a6 0x06 meaning reserved reserved dis10 dis5 dis4 dis3 reversed reserved default 0 0 0 1 1 1 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b b b b b b b b dis10 1 : ch10 would discharge vout10 node when it turns off. 0 : ch10 would not discharge vout10 node when it turns off. dis5 1 : ch5 would discharge vout5 node when it turns off. 0 : ch5 would not discharge vout5 node when it turns off. dis4 1 : ch4 would discharge vout4 node when it turns off. 0 : ch4 would not discharge vout4 node when it turns off. dis3 1 : ch3 would discharge vout3 node when it turns off. 0 : ch3 would not discharge vout3 node when it turns off. address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a7 0x07 meaning reserved reserved reserved reserved reserved ovp7 default 0 0 0 0 0 1 1 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b b b b b b b b ovp7 setting ch7 ovp threshold at vout7 node in step - up mode (range : 8v to 25v, default = 20v) code voltage code voltage code voltage code voltage 000 8v 010 12v 100 16v 110 20v 001 10v 011 14v 101 18v 111 25v address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a8 0x08 meaning reserved default 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b b b b b b b b reserved
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5035a/b - 02 february 2017 30 address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a9 0x09 meaning endly3 endly2 default decided by seq decided by seq read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b b b b b b b b endly3 setting endly3 for ch3 power on delay time (2ms x endly3). code voltage code voltage code voltage code voltage 0000 0ms 0100 8ms 1000 16ms 1100 24ms 0001 2ms 0101 10ms 1001 18ms 1101 26ms 0010 4ms 0110 12ms 1010 20ms 1110 28ms 0011 6ms 0111 14ms 1011 22ms 1111 30ms endly2 setting endly2 for ch2 power on delay time (2ms x endly2). code voltage code voltage code voltage code voltage 0000 0ms 0100 8ms 1000 16ms 1100 24ms 0001 2ms 0101 10ms 1001 18ms 1101 26ms 0010 4ms 0110 12ms 1010 20ms 1110 28ms 0011 6ms 0111 14ms 1011 22ms 1111 30ms address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a10 0x0a meaning endly10 endly4 default decided by seq decided by seq read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b b b b b b b b endly10 setting endly10 for ch10 power on delay time (2ms x endly10). code voltage code voltage code voltage code voltage 0000 0ms 0100 8ms 1000 16ms 1100 24ms 0001 2ms 0101 10ms 1001 18ms 1101 26ms 0010 4ms 0110 12ms 1010 20ms 1110 28ms 0011 6ms 0111 14ms 1011 22ms 1111 30ms endly4 setting endly4 for ch4 power on delay time (2ms x endly4). code voltage code voltage code voltage code voltage 0000 0ms 0100 8ms 1000 16ms 1100 24ms 0001 2ms 0101 10ms 1001 18ms 1101 26ms 0010 4ms 0110 12ms 1010 20ms 1110 28ms 0011 6ms 0111 14ms 1011 22ms 1111 30ms
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5035a/b - 02 february 2017 www.richtek.com 31 address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a11 0x0b meaning shdly3 shdly2 default decided by seq decided by seq read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b b b b b b b b shdly3 setting shdly3 for ch3 power off delay time (2ms x shdly3). code voltage code voltage code voltage code voltage 0000 0ms 0100 8ms 1000 16ms 1100 24ms 0001 2ms 0101 10ms 1001 18ms 1101 26ms 0010 4ms 0110 12ms 1010 20ms 1110 28ms 0011 6ms 0111 14ms 1011 22ms 1111 30ms shdly2 setting shdly2 for ch2 power off delay time (2ms x shdly2). code voltage code voltage code voltage code voltage 0000 0ms 0100 8ms 1000 16ms 1100 24ms 0001 2ms 0101 10ms 1001 18ms 1101 26ms 0010 4ms 0110 12ms 1010 20ms 1110 28ms 0011 6ms 0111 14ms 1011 22ms 1111 30ms address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a12 0x0c meaning shdly10 shdly4 default decided by seq decided by seq read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b b b b b b b b shdly10 setting shdly10 for ch10 power on delay time (2ms x shdly10). code voltage code voltage code voltage code voltage 0000 0ms 0100 8ms 1000 16ms 1100 24ms 0001 2ms 0101 10ms 1001 18ms 1101 26ms 0010 4ms 0110 12ms 1010 20ms 1110 28ms 0011 6ms 0111 14ms 1011 22ms 1111 30ms shdly4 setting shdly4 for ch4 power on delay time (2ms x shdly4). code voltage code voltage code voltage code voltage 0000 0ms 0100 8ms 1000 16ms 1100 24ms 0001 2ms 0101 10ms 1001 18ms 1101 26ms 0010 4ms 0110 12ms 1010 20ms 1110 28ms 0011 6ms 0111 14ms 1011 22ms 1111 30ms
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5035a/b - 02 february 2017 32 address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a13 0x0d meaning reserved reserved reserved reserved reserved reserved shdn_ pfm1 shdn_ pfm10 default 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b b b b b b b b shdn_pfm1 0 : ch1 is off when en is low (part. a default) 1 : ch1 operates at pfm when en is low (part. b default) shdn_pfm10 0 : ch10 is off when en is low 1 : ch 10 operates at pfm when en is low address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a14 0x0e meaning pwm1 ensw4 en4 en5 en6 en7 en8 pwm10 default 1 0 1 0 0 0 0 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition a a a a a a a a pwm1 1 : means ch1 in peak - current control pwm synchronous rectified operation mode. 0 : means ch1 in pfm asynchronous rectified operation mode. ensw4 1 : enable sw4. 0 : disable sw4 en4 1 : enable ch4 0 : disable ch4 en5 1 : enable ch5 0 : disable ch5 en6 1 : enable ch6 0 : disable ch6 en7 1 : enable ch7 0 : disable ch7 en8 1 : enable ch8 0 : disable ch8 pwm10 1 : means ch10 in peak - current control pwm synchronous rectified operation mode. 0 : means ch10 in pfm mode notes : ensw4, en4/5/6/7/8 at a 14 : enable (enx = 1) or disable (enx = 0) sw4/ch4/5/6/7/8 when en pin goes high, chx would turn on (after the delay time endlyx) if the bits enx = 1. the register byte a 14 would be reset when the external en input pin goes low.
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5035a/b - 02 february 2017 www.richtek.com 33 address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a15 0x0f meaning reserved reserved reserved reserved reserved reserved ss syn_div default 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition b b b b b b b b syn_div 0: freq of rt 5035a/b =freq of sync 1: freq of rt 5035a/b =freq of sync/6 ss 0: spread spectum off 1: spread spectum on address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a16 0x10 meaning reserved reserved reserved reserved dis9 bat_uvlo reserved default 0 0 0 0 0 1 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w reset condition c c c c c c c c dis9 0: no discharge vddm when batuvlo occurs. 1: discharge vddm when batuvlo occurs. bat_uvlo (li) bat uvlo setting voltage (range : 2.4v to 2.7v, default = 2.6v) (part. a) code voltage code voltage code voltage code voltage 00 2.4v 01 2.5v 10 2.6v 11 2.7v bat_uvlo (2aa) bat uvlo setting voltage (range : 1.7v to 2v, default = 1.7v) (part. b) code voltage code voltage code voltage code voltage 00 1.7v 01 1.8v 10 1.9v 11 2v address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a17 0x11 meaning reserved rtcaj default 0 0 1 1 1 1 0 0 read/write r r/w r/w r/w r/w r/w r/w r/w reset condition c c c c c c c c rtcaj finely tune the rtc time counting frequency by adjusting (rtcaj ? ?
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5035a/b - 02 february 2017 34 address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a18 0x12 meaning busy reversed rtct_sec default 0 0 0 0 0 0 0 0 read/write r r r/w r/w r/w r/w r/w r/w reset condition c c c c c c c c busy 1: rtc is busy and the writing access is not allowed rtct_sec[5:0] stores the second field of rtc time. that is 0 to 59. address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a19 0x13 meaning reversed reversed rtct_min default 0 0 0 0 0 0 0 0 read/write r r r/w r/w r/w r/w r/w r/w reset condition c c c c c c c c rtct_min[5:0] stores the minute field of rtc time. that is 0 to 59. address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a20 0x14 meaning mode_12h am/pm reversed rtct_hr default 0 0 0 0 0 0 0 0 read/write r/w r/w r r/w r/w r/w r/w r/w reset condition c c c c c c c c mode_12h/24h 0 = 24h, 1 = 12h am/pm 0 = am, 1 = pm rtct_hr[4:0] stores the hour field of rtc time. that is 0 to 23 (24hour format). address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a21 0x15 meaning reversed reversed rtct_year default 0 0 0 0 1 1 0 1 read/write r r/w r/w r/w r/w r/w r/w r/w reset condition c c c c c c c c rtct_y e ar[ 6 :0] stores the year field of rtc time. that is 0 to 63. rtct_y e ar = 0 means the year 2000. hence, rt 5035a/b can count till the year 2063.
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5035a/b - 02 february 2017 www.richtek.com 35 address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a22 0x16 meaning rtc month default reversed reversed reversed reversed rtct_mon read/write 0 0 0 0 0 0 0 1 reset condition c c c c c c c c rtct_mon [3:0] stores the month field of rtc time. that is 1 to 12. rtct_mon = 1 means january. address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a23 0x17 meaning rtct_week rtct_day default 1 1 0 0 0 0 0 1 read/write r r r r/w r/w r/w r/w r/w reset condition c c c c c c c c rtct_wek [2:0] stores the day - of - week field of rtc time. that is 0 to 6. rtct_wek = 0 means sunday. rtct_wek = 1 means monday. rt 5035a/b cannot calculate automatically the field based on other fields. (year, month, date). rtct_day[4:0] stores the date field of rtc time. that is 1 to 31, depending on the month. rtct_day [4:0] = 1 means 1st day of each month. rt 5035a/b supports leap year counting. address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a24 0x18 meaning user[7:0] default 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r/w r/w r/w r/w reset condition c c c c c c c c a25 0x19 meaning user[15:8] default 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r/w r/w r/w r/w reset condition c c c c c c c c a26 0x1a meaning user[23:16] default 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r/w r/w r/w r/w reset condition c c c c c c c c
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5035a/b - 02 february 2017 36 address name register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a27 0x1b meaning user[31:24] default 0 0 0 0 0 0 0 0 read/write r r/w r/w r/w r/w r/w r/w r/w reset condition c c c c c c c c user[31:0] user[31:0] at a24 to a27: stores user's data. it is like a sarm, which accesses via i 2 c. reset condition a external en pin goes low . b a0 to a13 and a15 : reset when ( = l) occurs . c a16 to a27: reset when rtc reset occurs. reset
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5035a/b - 02 february 2017 www.richtek.com 37 output voltage list i 2 c register value vout1 4bit vout2 4bit vout3 4bit vout4 4bit vout5 3bit vout6 4bit vout8 3bit vout10 3bit 0 5.3 3.65 1.3 2.14 2 3 5.2 1.52 1 5.2 3.6 1.28 2.1 1.8 2.9 5.1 1.5 2 5.1 3.55 1.26 2.06 1.5 2.8 * 5 1.37 3 5 3.5 1.24 2.04 1.35 * 2.7 3.5 1.35 4 4.9 3.45 1.22 2 1.26 2.6 3.4 1.25 5 4.8 3.4 1.2 1.96 1.23 2.5 3.3 1.22 6 4.7 3.35 1.18 1.92 * 1.2 2.4 3 1.2 7 4.6 3.3 1.16 1.88 ref (0.8) 2.3 1.5 ref (0.8) 8 4.5 * 3.25 1.14 1.84 2.2 9 4.4 3.2 1.12 * 1.8 2 10 4.3 3.15 1.1 1.76 1.9 11 4.2 3.1 1.06 1.54 1.8 12 4 3.05 1.04 1.5 1.7 13 3.9 3 1.02 1.46 1.5 14 3.8 2.95 1 1.39 1.4 15 * 3.6 2.9 ref (0.8) 1.35 1.2 * : default value vout 3 / 4 / 10 default voltage is selected by the seq pin and latched at the moment w hen goes high. seq id the seq pin pull down resistance r seq defines power on/off sequence and default voltage . seq id r seq range ( k ? ) typical r seq ( k ? ) p ower on p rocedure seq #0 conne c t to power (>0.2v, < avdd ) before en goes high reserved seq #1 80 > r seq >20 40 refer table. seq1 seq #2 20 > r seq >5 10 refer table. seq2 seq #3 5 > r seq >1.25 2.5 refer table. seq3 seq #4 1.25 > r seq or connect to gnd (<0.2v) 0.625 or short to gnd refer table. seq4 seq #5 r seq >80 or floating (hz) 120 or hz refer table. seq5 seq1 register item code value a2 vout3 1101 1.02 v a2 vout4 1001 1.8v a5 vout10 111 ref a9 endly3 0111 14ms a9 endly2 10 11 22 ms a10 endly10 100 1 18 ms a10 endly4 100 1 18 ms a11 shdly3 1010 20ms a11 shdly2 0000 0ms a12 shdly10 0000 0ms a12 shdly4 0000 0ms reset
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5035a/b - 02 february 2017 38 seq2 register item code value a2 vout3 1101 1.02v a2 vout4 1001 1.8v a5 vout10 101 1.22v a9 endly3 0111 14ms a9 endly2 1001 18 ms a10 endly10 1001 1 8 ms a10 endly4 1001 18ms a11 shdly3 1010 20ms a11 shdly2 0000 0ms a12 shdly10 0000 0ms a12 shdly4 0000 0ms seq3 register item code value a2 vout3 1111 ref a2 vout4 1001 1.8v a5 vout10 111 ref a9 endly3 0111 14ms a9 endly2 1001 18ms a10 endly10 100 1 18 ms a10 endly4 1001 18ms a11 shdly3 1010 20ms a11 shdly2 0000 0ms a12 shdly10 0000 0ms a12 shdly4 0000 0ms seq4 register item code value a2 vout3 1000 1.14v a2 vout4 1001 1.8v a5 vout10 011 1.35v a9 endly3 0111 14ms a9 endly2 100 1 1 8 ms a10 endly10 1001 1 8 ms a10 endly4 1001 18ms a11 shdly3 1010 20ms a11 shdly2 0000 0ms a12 shdly10 0000 0ms a12 shdly4 0000 0ms seq5 register item code value a2 vout3 1101 1.02 v a2 vout4 1001 1.8v a5 vout10 011 1. 35 v a9 endly3 0111 14ms a9 endly2 1001 18ms a10 endly10 100 1 1 8 ms a10 endly4 100 1 1 8 ms a11 shdly3 1010 20ms a11 shdly2 0000 0ms a12 shdly10 0000 0ms a12 shdly4 0000 0ms
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5035a/b - 02 february 2017 www.richtek.com 39 thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding ai rflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ? ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ? ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 ? c. the junction to ambient thermal resistance, ? ja , is layout dependent. for wqfn - 40l 5x5 package, the thermal re sistance, ? ja , is 27.5 ? c/w on a standard jedec 51 - 7 four - layer thermal test board. the maximum power dissipation at t a = 25 ? c can be calculated by the following formula : p d(max) = (125 ? c ? 25 ? c) / ( 27.5 ? c/w) = 3.63 w for wqfn - 40 l 5 x 5 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ? ja . the derating curve in figure 1 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 1 . derating curve of maximum power dissipation layout considerations the pcb layout is an important step to maintain the high performance of the rt 5035a/b . both the high current and the fast switching nodes demand full attention to the pcb layout to save the robustness of the rt 5035a/b through the pcb layout. improper layout might show the symptoms of poor line or load regulation, ground and output voltage shifts, stability issues, unsatisfying emi behavior or worsened efficiency. for the best performance of the rt 5035a/b , the following pcb layout guidelines must be strictly followed . ? place the input and output capacitor s as close as possible to the input and output pins respectively for good filtering. ? keep the main power traces as wide and short as possible. ? the switching node area connected to lx and inductor should be minimized for lower emi. ? place the feedback compon ents as close as possible to the fb pin and keep these components away from the noisy devices. ? connect the gnd and exposed pad to a strong ground plane for maximum thermal dissipation and noise protection. ? directly connect the output capacitors to the feed back network of each channel to avoid bouncing caused by parasitic resistance and inductance fr om the pcb trace. ? f or the 32 - khz oscillator to the best performance, observe the following guidelines : ? place the crystal and its components close to the oscilla tor side and the oscillator pins. ? ensure that the ground plane under the oscillator and its components are of good quality. ? avoid placing a separate ground under the oscillator and connecting it to the general ground through a single point. ? avoid long conn ections to the crystal and to the load capacitor that create a large loop on the pcb . ? use a short connection between the two crystal load capacitors and route the common connection to the oscillator ground reference. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5035a/b - 02 february 2017 40 ? place a ceramic capacitor for noise fil tering from rtc pwr to rtc gnd with short connections. ? place the c 32 k (logic output signal) output so that the return ground current runs back to rtc gnd. do not route the trace close to the oscillator input. figure 2 . pcb layout guide 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 l x 1 / r e s e t f b 7 v o u t 6 p v d d 6 l x 7 l x 4 p v d d 4 / 1 0 l x 1 0 v n e g c n c p b a t v o u t 1 0 / f b 1 0 s w o s e q l x 3 p v d d 8 v o u t 8 p v d d 5 l x 5 p v d d 2 l x 2 a e n l x 2 b v o u t 1 s y n c r t c p w r x i n x o u t r t c g n d s c l s d a v o u t 2 v o u t 3 / f b 3 p v d d 3 c 3 2 k l 1 y 1 c r t c p w r c x o u t c x i n l 3 c o u t 3 d 1 d 2 c o u t 8 l 5 c i n 2 l 2 c s w o c o u t 2 r s d a r s c l l 4 l 7 c i n 1 c v d d m c o u t 5 v o u t _ c h 1 v o u t _ c h 4 v o u t _ c h 2 v d d m b a t g n d g n d g n d l x s h o u l d b e c o n n e c t e d t o i n d u c t o r b y w i d e a n d s h o r t t r a c e , k e e p s e n s i t i v e c o m p o n t e n t s a w a y f r o m t h i s t r a c e . g n d c o n n e c t t h e e x p o s e d p a d t o a g r o u n d p l a n e . i n p u t / o u t p u t c a p a c i t o r s m u s t b e p l a c e d a s c l o s e a s p o s s i b l e t o t h e i n p u t / o u t p u t p i n s . d 3 c o u t 1 g n d v o u t 5 / f b 5 c i n 3 v o u t _ c h 3 c i n 8 c o u t 2 c c p c i n 4 c o u t 4 d 4 c o u t 6 v o u t _ c h 8 v o u t _ c h 5 c i n 5 g n d g n d t h e g r o u n d s u r r o u n d e d c 3 2 k p i n a n d k e e p a w a y f r o m n o i s y d e v i c e s . r r t c p w r b a c k u p b a t t e r y c o u t 1 0 v o u t _ c h 1 0 c o u t 1 s w o r e x t c v n e g b a t c i n 6 / 7 b a t b a t b a t v o u t _ c h 1 r s e q v o u t 4 / s w i c b a t b a t l 1 0 d 5 d 6 c o u t 7 d 7
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5035a/b - 02 february 2017 www.richtek.com 41 max load of every channel purpose rt 5035a/b c urrent l imit m ax l oad c ondition (v in v out ) vddm and v motor ch1 3.5a 1200ma 3v 5v vi/o ch2 3a 900ma 3v 3.3v vcore ch3 3a 2a 3v 1.1v vmem ch4 1.5a 700ma 3v 1.8v cmos_d ch5 1.5a 500ma 3v 2.2v cmos_a ch6 450ma 300ma 3v 2.7v load sw sw4 900ma 500ma 1.8v 1.8v wled ch7 0.8a 30ma 6 wled generic ldo ch8 300ma 200ma v in ? v out > 150mv keep - alive ldo ch9 100ma 50ma vin ? ? vout > 300mv vmem ch10 1.5a 700ma 3v 1.35v protection act protection t ype threshold ( t ypical value ) delay t ime protection m ethod reset m ethod vddm over voltage protection vddm > 6 v 100ms turn off whole ic, except ch9 and ch1 in pfm ( only for 2aa) restart if vddm < 5. 8 v bat uvlo v bat < 2.4v ( RT5035A ) no delay disable all channels restart if v bat > 2.6v ( RT5035A ), v bat > 1.7v ( rt5035b ) v bat < 1.5v ( rt5035b ) ch1 current limit (in pfm ) nmos current > 0.8 a no delay t u rn off nmos r eset after min - off - time finish vout1 ovp (in pwm) vout1 > 5.8 v 100ms turn off whole ic, except ch9 and ch1 in pfm ( only for 2aa) vddm power reset or en = low ocp (in pwm) nmos current > 3 .5 a 100ms turn off whole ic, except c h 9 and c h 1 in pfm ( only for 2aa) vddm power reset or en = low vout1 uvp (in pwm) vout1< 2.25v no delay turn off whole ic, except c h 9 and c h 1 in pfm ( only for 2aa) vddm power reset or en = low over - l oad protection (in pwm) vout1 < target ? 0.6 v 100ms turn off whole ic, except c h 9 and c h 1 in pfm ( only for 2aa) vddm power reset or en = low
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5035a/b - 02 february 2017 42 protection t ype threshold ( t ypical value ) delay t ime protection m ethod reset m ethod ch2 ocp inductor current > 3 a no delay turn off whole ic, except c h 9 and c h 1 in pfm ( only for 2aa) vddm power reset or en = low vout2 ovp vout2 > 6v no delay turn off whole ic, except c h 9 and c h 1 in pfm ( only for 2aa) vddm power reset or en = low vout2 uvp vout2 < 1.6v no delay turn off whole ic, except c h 9 and c h 1 in pfm ( only for 2aa) vddm power reset or en = low over - l oad protection vout2 < target ? ? 0.4v 100ms turn off whole ic, except c h 9 and c h 1 in pfm ( only for 2aa) vddm power reset or en = low ch3 ocp pmos current > 3 a 100ms turn off whole ic, except c h 9 and c h 1 in pfm ( only for 2aa) vddm power reset or en = low vout3 uvp vout3 < 0.6 v no delay turn off whole ic, except c h 9 and c h 1 in pfm ( only for 2aa) vddm power reset or en = low over - l oad protection vout3 < target C 0.15 v 100ms turn off whole ic, except c h 9 and c h 1 in pfm ( only for 2aa) vddm power reset or en = low ch4 ocp pmos current > 1.5 a 100ms turn off whole ic, except c h 9 and c h 1 in pfm ( only for 2aa) vddm power reset or en = low vout4 uvp vout4 < 0.8v no delay turn off whole ic, except c h 9 and c h 1 in pfm ( only for 2aa) vddm power reset or en = low over - l oad protection vout4 < target ? ? 0.2 v 100ms turn off whole ic, except c h 9 and c h 1 in pfm ( only for 2aa) vddm power reset or en = low ch5 ocp p mos current > 1. 5 a 100ms turn off whole ic, except c h 9 and c h 1 in pfm ( only for 2aa) vddm power reset or en = low vout 5 uvp vout 5 < 0.8v no delay turn off whole ic, except c h 9 and c h 1 in pfm ( only for 2aa) vddm power reset or en = low over - l oad protection vout 5 < target ? ? 0.2 v 100ms turn off whole ic, except c h 9 and c h 1 in pfm ( only for 2aa) vddm power reset or en = low c h6 uvp a2.vout6 = 0 to 9, vout6<1.6v a2.vout6 = 10 to 15, vout6 < 0.8v no delay turn off whole ic, except ch9 and ch1 in pfm ( only for 2aa) vddm power reset or en = low current limit pmos current > 45 0ma no delay limit pmos current reset by load
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. ds5035a/b - 02 february 2017 www.richtek.com 43 protection t ype threshold ( t ypical value ) delay t ime protection m ethod reset m ethod ch7 ocp nmos current > 0.8a 100ms t urn o ff whole ic vddm power reset or en = low ovp lx7 > a4.ovp7 threshold no delay turn o ff ch7 only vddm power reset or en = low c h 8 uvp vout8 < target x 0.5 no delay turn off whole ic, except c h9 and c h1 in pfm ( only for 2aa) vddm power reset or en = low current limit pmos current > 300ma no delay limit pmos current reset by load ch9 current limit pmos current > 10 0ma no delay limit pmos current reset by load vddm uvlo v ddm < 2. 2 v no delay turn off whole ic, except c h9 and c h1 in pfm r estart whole ic if en = high and v ddm > 2.4 v v ddm < 2. 2 v no delay goes low r estart whole ic if en = high and v ddm > 2. 4 v ch 10 ocp pmos current > 1.5 a 100ms turn off whole ic, except ch9 and ch1 in pfm ( only for 2aa) vddm power reset or en = low vout 10 uvp vout 10 < 0.8v no delay turn off whole ic, except c h9 and ch1 in pfm ( only for 2aa) vddm power reset or en = low over - l oad protection vout 10 < target ? 0.2 v 100ms turn off whole ic, except ch9 and ch1 in pfm vddm power reset or en = low rtc pwr uvlo rtcpwr < 1. 9 v no delay c lear rtc regist e rs rtcpwr > 2.2 v sw4 load switch uvp swo < swi ? 0.9v o r swo < 0.9v no delay turn off whole ic, except ch9 and ch1 in pfm ( only for 2aa) vddm power reset or en = l current limit n mos current > 9 00ma no delay limit n - mosfet current reset by load thermal thermal shutdown temperature > 160 ? c no delay turn off whole ic, except ch9 and ch1 in pfm ( only for 2aa) r estart whole ic if en = high and temperature < 140 ? c reset
rt 5035a/b copyright ? 2017 richtek technology corporation. all rights reserved. is a registered trademark of richtek technology corporation. www.richtek.com ds5035a/b - 02 february 2017 44 outline dimension symbol dimensions in millimeters dimensions in inches min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 4.950 5.050 0.195 0.199 d2 3.250 3.500 0.128 0.138 e 4.950 5.050 0.195 0.199 e2 3.250 3.500 0.128 0.138 e 0.400 0.016 l 0.350 0.450 0.014 0.018 w - type 40l qfn 5x5 package richtek technology corporation 14f, no. 8, tai yuen 1 st street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications witho ut notice at any time. customers should obtain the latest relevant informat ion and data sheets before placing orders and should verify that such information is current and complete. richtek cannot ass ume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnished by r ichtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringements of pate nts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of richtek or its subsidiaries.

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